tsmc's a14 node: a calculated step back or a strategic advantage for intel?

2025-04-30 tsmc

Taipei, Wednesday, 30 April 2025.
tsmc’s upcoming a14 (1.4nm) process might forego high-na euv lithography. this decision, driven by cost considerations, could see tsmc sticking with traditional 0.33 numerical aperture euv technology. the move could potentially hand intel, which is aggressively pursuing high-na euv, a competitive edge. while tsmc aims for cost efficiency, the industry watches closely to see if this choice impacts their ability to maintain its lead in cutting-edge chip manufacturing as samsung is expected to commercially implement high-na euv by late 2025.

cost versus competition: tsmc’s strategic choice

The decision to forgo high-NA EUV for the A14 node reflects a calculated trade-off [7]. TSMC’s Senior Vice President Kevin Zhang stated the company can maintain similar processing complexity without high-NA EUV for the A14 process, which is slated for production in 2028 [2][5]. He emphasized the importance of cost-efficient solutions [2][8]. TSMC estimates that using High-NA EUV could increase manufacturing costs by up to 2.5 times [2][4][7]. This move allows TSMC to keep production costs down, but it also risks ceding a technological advantage to competitors like Intel and Samsung [7].

intel’s high-na euv push and market implications

Intel is set to utilize high-NA EUV for its 18A process as early as next year [2][4]. This positions Intel to potentially leapfrog TSMC in terms of technology [7]. The price of a high-NA EUV machine is approximately $380 million, more than double the $180 million of the previous generation [5]. Intel already has two High-NA EUV machines in production, processing 30,000 wafers per quarter [4]. This aggressive adoption strategy signals Intel’s intent to regain market share and technological leadership, potentially impacting TSMC’s stock performance if investors perceive a weakening of TSMC’s competitive edge [GPT].

manufacturing capacity and geopolitical considerations

TSMC’s global expansion, particularly in the U.S., is under scrutiny. Kuomintang legislator Niu Xuting questioned the government about potential supply chain relocation following the establishment of TSMC’s U.S. factories [1]. Economic Minister Kuo Chih-hui responded that TSMC’s current production capacity is insufficient to induce a supply chain shift to the U.S., but this could change if TSMC builds all six planned wafer fabs there [1]. Taiwan’s government is also implementing measures to prevent key technology outflow, requiring prior application for investments exceeding a certain amount in specific countries, industries, or technologies [1][7].

tsmc’s future roadmap and a14p

While TSMC is skipping high-NA EUV for the initial A14 node, the company plans to introduce it with the A14P node, which is targeted for 2029 [2][4][5][8]. The A14P process will also feature backside power distribution [5][6][8]. This suggests that TSMC views high-NA EUV as essential for future performance enhancements, but not critical for the initial A14 rollout [2]. Financial analysts predict TSMC’s revenue growth in the second half of 2025 may slow to 5.7% compared to the first half [1]. The delay in high-NA EUV adoption could contribute to this slowdown if customers prioritize performance over cost [alert! ‘analyst predictions are subject to change’] [GPT].

Bronnen

TSMC EUV Lithography