intel casts doubt on asml's high-na euv: a chipmaking paradigm shift?

2025-06-23 asml

Eindhoven, Monday, 23 June 2025.
an intel director suggests asml’s high-na euv lithography might not dominate future chipmaking as expected. new transistor architectures and etching advancements could reduce reliance on these machines. tsmc might delay high-na euv adoption, while samsung is already pushing back its plans for dram. this shift could impact asml’s revenue and stock, as chinese firms advance in etching, potentially reshaping semiconductor manufacturing.

the intel director’s perspective

An anonymous Intel director suggested that future chip manufacturing will rely less on advanced lithography and more on etching techniques [1][3][6]. This perspective, revealed on the Tegus investment research platform, indicates that emerging transistor architectures like GAAFET (Gate-All-Around Field-Effect Transistor) and CFET (Complementary Field-Effect Transistor) could diminish the necessity for leading-edge lithography [1][3]. The director emphasized that these three-dimensional structures reduce dependence on minimal feature sizes, achieving high density through vertical stacking [2][3].

tsmc and samsung’s evolving strategies

Taiwan Semiconductor Manufacturing Co. (TSMC) may delay adopting High-NA EUV for its A14 process, continuing with 0.33-NA EUV, though they plan to use High-NA EUV for the A14P node [1]. Samsung Electronics is also reportedly delaying the adoption of ASML’s high-NA EUV lithography equipment in their DRAM production [1]. This shift in strategy by major players could signal a broader industry trend, impacting ASML’s order book and future revenue projections [alert! ‘specific revenue impact not quantified in provided sources’] [1].

etching technology gains prominence

The Intel director’s statement underscores the rising importance of etching in semiconductor manufacturing [3]. Etching involves selectively removing materials to form transistor structures, a process that becomes crucial with GAAFET and CFET architectures [3]. Chinese companies like Naura Technology, SiCarrier, and AMEC are making strides in etching tools, potentially contributing to China’s semiconductor self-sufficiency goals [1]. AMEC Chairman Gerald Yin noted that 5nm nodes can be achieved using DUV lithography coupled with advanced etching [1].

potential impact on asml’s market position

The reduced reliance on ASML’s high-NA EUV equipment could challenge its technological leadership and market position [1]. ASML’s EUV lithography machines, costing nearly $400 million each, have been pivotal in advancing chip manufacturing [7]. Christopher Bottoms, an IBM researcher, highlighted the challenges of stitching multiple masks in advanced lithography processes [7][8]. Zachary Levinson from Synopsys estimates that a 2nm mask-to-mask overlay error could lead to a 10% error in the printed pattern’s critical dimension [8].

challenges and alternative approaches

Achieving optimal results with High-NA EUV requires innovative manufacturing methods, including circuit stitching or larger masks [5]. Harry Levinson, President of HJL Lithography, estimates that halving the exposure field could reduce yield by up to 40% [8]. Frank Abboud, VP at Intel, suggested increasing mask sizes to address throughput issues, noting ASML’s platforms can accommodate 6x11.2-inch masks [8]. While larger masks could mitigate some challenges, they would also necessitate significant infrastructure changes and increased costs [5][8].

Bronnen

Chip Manufacturing ASML EUV