cadencelive silicon valley: see nvidia, google, intel chiefs unveil ai chip design

2025-05-07 general

Santa Clara, Wednesday, 7 May 2025.
cadencelive silicon valley 2025 convenes today, may 7th, at the santa clara convention center. industry titans from nvidia, google, and intel are set to reveal cutting-edge electronic design automation (eda) tools and semiconductor ip. a keynote fireside chat with nvidia ceo jensen huang and cadence ceo anirudh devgan promises insights. samsung touts a 50% reduction in simulation turnaround time using cadence tools. ibm research showcases an 80% wns reduction. don’t miss agentic ai for chip design by cadence’s charles alpert.

ai-driven innovation takes center stage

CadenceLIVE Silicon Valley 2025 highlights AI’s transformative role in electronic design [1]. Anirudh Devgan, Cadence’s CEO, and Jensen Huang, NVIDIA’s CEO, are engaging in a fireside chat, setting the stage for discussions on AI, 3D-IC, and chiplets [1][4]. Uri Frank from Google-ML is delivering a keynote on “The AI Hypercomputer” [1][4]. These sessions provide insights into how AI is reshaping chip design and potentially impacting the stock valuations of companies investing in these technologies [GPT].

cadence unveils millennium m2000 supercomputer

Cadence has introduced the Millennium M2000 Supercomputer, powered by NVIDIA Blackwell systems [7]. This supercomputer achieves up to 80 times the performance of CPU-based systems while using up to 20 times less power [7]. The Millennium M2000 is designed for AI-accelerated simulation in semiconductor design, 3D-IC development, and drug discovery [7]. Anirudh Devgan emphasizes that the M2000 will drive the next leap in AI-accelerated engineering [7]. This innovation could significantly improve Cadence’s competitive edge and attract investors [GPT].

samsung and intel showcase efficiency gains with cadence

Samsung’s case study reveals a 50% reduction in EMIR simulation turnaround time using Cadence’s XM-Based Hierarchical Modeling on advanced node designs [4]. This efficiency gain came with less than 1% accuracy loss without package considerations and a 5% accuracy loss with package inclusion [4]. Srinivasu Parla from Intel Corporation highlights a 50% improvement in layout productivity using Virtuoso Studio for node-to-node layout migration [4]. These improvements can lead to faster product cycles and cost savings, positively impacting the financial performance of Samsung and Intel [GPT].

celus integrates with cadence orcad x for enhanced pcb design

CELUS has integrated its AI-powered Design Platform with Cadence’s OrCAD X Platform [8]. This integration aims to provide engineers with AI-driven advice and a user-friendly design experience, accelerating the hardware design process [8]. Tobias Pohl, CEO of CELUS, notes that this partnership represents a significant leap forward in hardware design automation [8]. The integration could attract more users to the Cadence ecosystem and boost the value of OrCAD X [GPT].

agentic ai and nvidia’s llama nemotron

Charles Alpert from Cadence Design Systems is presenting on harnessing Agentic AI for chip design [4]. NVIDIA proposes using its Llama Nemotron model as a central reasoning unit, complemented by Cadence’s software, to automate and enhance the design process [4]. Zijian Du from NVIDIA presented on automating electronic design with the NVIDIA Llama Nemotron Reasoning Model [4]. This collaboration between Cadence and NVIDIA could lead to new AI-driven solutions, potentially increasing the appeal of both companies to investors [GPT].

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semiconductor design eda tools