Intel's packaging tech: a path to monolithic ai chips?
Santa Clara, Monday, 9 June 2025.
As Moore’s Law slows, Intel is innovating new chip packaging, which could mean larger, more powerful AI chips by 2025. The upgraded tech allows for more than 10,000 square millimeters of silicon to be integrated into a single package. This advancement aims to improve signal exchange, effectively creating a single, giant chip. The move is set to intensify competition with NVIDIA and TSMC, potentially reshaping the high-stakes AI landscape.
Inside intel’s advanced packaging
Intel’s newly revealed packaging technology includes three key innovations [1]. These are improvements to linking silicon dies, a method for silicon bonding to the package substrate, and a system that expands heat removal [1]. The new technologies facilitate the integration of over 10,000 square millimeters of silicon within a package exceeding 21,000 square millimeters [1]. Intel’s EMIB technology, which embeds a sliver of silicon in the organic package, is crucial for connecting silicon dies [1]. The company recently introduced EMIB-T, featuring through-silicon vias (TSVs) and a copper grid to enhance power delivery and reduce noise [1].
emib-t details and benefits
EMIB-T allows customers to connect silicon equivalent to over 12 full-size silicon dies, or 10,000 square millimeters, in a single package using 38 or more EMIB-T bridges [1]. Intel is also working on low-thermal-gradient thermal compression bonding to increase package sizes [1]. This advancement allows for connections to EMIB down to about one every 25 micrometers [1]. To manage the heat generated by these larger packages, Intel is assembling the integrated heat spreader in parts [1]. According to Rahul Manepalli, Intel’s VP of substrate packaging technology, maintaining flatness at higher temperatures significantly benefits reliability and yield [1].
competitive landscape and market impact
Intel’s advanced packaging technology aims to allow Intel Foundry to better compete with TSMC’s packaging expansions [1]. These technologies are currently in the research and development phase and are expected to debut in the coming years [1]. As the sole CPU Socket supplier in mainland China certified by Intel, Derun Electronics’ products are used in the packaging of computing chips from NVIDIA and Intel [6]. Their products directly impact the stability of chip signal transmission [6]. The company’s quantum chip connectors can reduce signal delay by 30%, promoting modular quantum computing development [6].
investment perspective
From an investor’s perspective, Intel’s advancements in chip packaging are a strategic move to maintain competitiveness in the face of slowing Moore’s Law [1]. The ability to integrate more silicon into a single package can lead to higher performance AI chips, potentially increasing Intel’s market share and stock value [1]. Successful implementation of EMIB-T and related technologies could attract significant investment and drive revenue growth. However, investors should monitor the progress of these technologies as they move from R&D to commercial deployment, especially against competitors like TSMC and NVIDIA [3][4].